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19-3591; Rev 0; 2/05
KIT ATION EVALU BLE AVAILA
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
General Description
The MAX5878 is an advanced 16-bit, 250Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 76dBc spurious-free dynamic range (SFDR) at fOUT = 16MHz and supports update rates of 250Msps, with a power dissipation of only 296mW. The MAX5878 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and allows a 0.1VP-P to 1VP-P differential output voltage swing. The device features an integrated +1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy. The clock inputs of the MAX5878 accept both LVDS and LVPECL-compatible voltage levels. The device features an interleaved data input that allows a single LVDS bus to support both DACs. The MAX5878 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended temperature range (-40C to +85C). Refer to the MAX5876* and MAX5877* data sheets for pin-compatible 12-bit and 14-bit versions of the MAX5878, respectively. Refer to the MAX5875 data sheet for a CMOS-compatible version of the MAX5878. 250Msps Output Update Rate Noise Spectral Density = -164dBFS/Hz at fOUT = 16MHz Excellent SFDR and IMD SFDR = 76dBc at fOUT = 16MHz (to Nyquist) SFDR = 71dBc at fOUT = 80MHz (to Nyquist) IMD = -90dBc at fOUT = 10MHz IMD = -72dBc at fOUT = 80MHz ACLR = 75dB at fOUT = 61MHz 2mA to 20mA Full-Scale Output Current LVDS-Compatible Digital and Clock Inputs On-Chip +1.20V Bandgap Reference Low 296mW Power Dissipation Compact 68 QFN-EP Package (10mm x 10mm) Evaluation Kit Available (MAX5878EVKIT)
Features
MAX5878
Ordering Information
PART MAX5878EGK TEMP RANGE -40C to +85C PINPACKAGE 68 QFN-EP** PKG CODE G6800-4
**EP = Exposed pad.
Pin Configuration
TOP VIEW
DVDD1.8 B10N B11N B12N B10P B11P B5N B6N B7N B8N B9N B4P B5P B6P B7P B8P B9P
Applications
Base Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave Direct Digital Synthesis (DDS) Cable Modem Termination Systems (CMTS) Automated Test Equipment (ATE) Instrumentation
*Future product--contact factory for availability.
B4N B3P B3N B2P B2N B1P B1N B0P B0N GND DVDD3.3 GND GND AVDD3.3 GND REFIO FSADJ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
B12P B13N B13P B14N B14P B15N B15P SELIQN SELIQP XORP XORN PD TORB CLKP CLKN GND AVCLK
Selector Guide
PART MAX5873 MAX5874 MAX5875 MAX5876* MAX5877* MAX5878 RESOLUTION (BITS) 12 14 16 12 14 16 UPDATE RATE 200Msps 200Msps 200Msps 250Msps 250Msps 250Msps LOGIC INPUTS CMOS CMOS CMOS LVDS LVDS LVDS
MAX5878
42 41 40 39 38 37 36 35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AVDD1.8
GND
OUTQN
OUTQP
GND
GND
OUTIN
OUTIP
GND
DACREF
AVDD3.3
AVDD3.3
GND
AVDD3.3
AVDD3.3
GND
QFN
________________________________________________________________ Maxim Integrated Products
AVDD1.8
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
ABSOLUTE MAXIMUM RATINGS
AVDD1.8, DVDD1.8 to GND, DACREF...................-0.3V to +2.16V AVDD3.3, DVDD3.3, AVCLK to GND, DACREF ........-0.3V to +3.9V REFIO, FSADJ to GND, DACREF..................................-0.3V to (AVDD3.3 + 0.3V) OUTIP, OUTIN, OUTQP, OUTQN to GND, DACREF..................-1V to (AVDD3.3 + 0.3V) CLKP, CLKN to GND, DACREF.............-0.3V to (AVCLK + 0.3V) B15P/B15N-B0P/B0N, XORN, XORP, SELIQN, SELIQP to GND, DACREF ..................-0.3V to (DVDD1.8 + 0.3V) TORB, PD to GND, DACREF ..............-0.3V to (DVDD3.3 + 0.3V) Continuous Power Dissipation (TA = +70C) 68-Pin QFN-EP (derate 41.7mW/C above +70C) (Note 1) ............3333.3mW Thermal Resistance JA (Note 1)...................................+24C/W Operating Temperature Range ......................... -40C to +85C Junction Temperature .................................................... +150C Storage Temperature Range ........................... -60C to +150C Lead Temperature (soldering, 10s) ............................... +300C
Note 1: Thermal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, output load 50 double-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Drift Tempco Full-Scale Gain Error Gain-Drift Tempco Full-Scale Output Current Output Compliance Output Resistance Output Capacitance DYNAMIC PERFORMANCE Clock Frequency Output Update Rate Noise Spectral Density fCLK fDAC fDAC = 150MHz fDAC = 250MHz fOUT = 16MHz, -12dBFS fOUT = 80MHz, -12dBFS 2 1 -164 -161 500 250 MHz Msps dBFS/ Hz ROUT COUT IOUTFS GEFS External reference Internal reference External reference (Note 3) Single-ended 2 -0.5 1 5 -4.1 INL DNL OS Measured differentially Measured differentially -0.015 16 3 2 0.001 10 -0.6 100 50 20 +1.1 +4.1 +0.015 Bits LSB LSB %FS ppm/C %FS ppm/C mA V M pF SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, output load 50 double-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS fOUT = 1MHz, 0dBFS fOUT = 1MHz, -6dBFS fDAC = 100MHz fOUT = 1MHz, -12dBFS fOUT = 10MHz, -12dBFS fOUT = 30MHz, -12dBFS fOUT = 10MHz, -12dBFS Spurious-Free Dynamic Range to Nyquist SFDR fOUT = 16MHz, -12dBFS, TA +25oC fOUT = 16MHz, -12dBFS fOUT = 50MHz, -12dBFS fOUT = 80MHz, -12dBFS fOUT = 10MHz, -12dBFS fDAC = 250MHz fOUT = 50MHz, -12dBFS fOUT = 80MHz, -12dBFS fOUT = 100MHz, -12dBFS Spurious-Free Dynamic Range, 25MHz Bandwidth SFDR fDAC = 150MHz fDAC = 100MHz Two-Tone IMD TTIMD fDAC = 200MHz Four-Tone IMD, 1MHz Frequency Spacing, GSM Model Adjacent Channel Leakage Power Ratio 3.84MHz Bandwidth, W-CDMA Model Output Bandwidth INTER-DAC CHARACTERISTICS Gain Matching Gain-Matching Tempco Phase Matching Phase-Matching Tempco Channel-to-Channel Crosstalk REFERENCE Internal Reference Voltage Range VREFIO 1.14 1.2 1.26 V Gain Gain/C Phase fOUT = 60MHz Phase/C fOUT = 60MHz fCLK = 400MHz, fOUT = 50MHz, 0dBFS fOUT = DC - 80MHz fOUT = DC -0.22 0.2 +0.01 20 0.25 0.002 86 +0.22 dB ppm/C Degrees Degrees/ C dB FTIMD fDAC = 150MHz fDAC = 184.32MHz (Note 4) fOUT = 16MHz, -12dBFS fOUT1 = 9MHz, -7dBFS; fOUT2 = 10MHz, -7dBFS fOUT1 = 79MHz, -7dBFS; fOUT2 = 80MHz, -7dBFS fOUT = 16MHz, -12dBFS 69 67 MIN TYP 94 87 81 81 79 75 76 76 73 71 74 75 71 69 78 -90 dBc -72 -80 dBc dBc dBc MAX UNITS
MAX5878
fDAC = 200MHz
ACLR BW-1dB
fOUT = 61.44MHz
75 240
dB MHz
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3
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, output load 50 double-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Reference Input Compliance Range Reference Input Resistance Reference Voltage Drift Output Fall Time Output Rise Time Output Propagation Delay Glitch Impulse Output Noise TIMING CHARACTERISTICS Data to Clock Setup Time Data to Clock Hold Time Data Latency Minimum Clock Pulse-Width High Minimum Clock Pulse-Width Low Differential Input-Logic High Differential Input-Logic Low Common-Mode Voltage Range Differential Input Resistance Input Capacitance CMOS LOGIC INPUTS (PD, TORB) Input-Logic High Input-Logic Low Input Leakage Current PD, TORB Internal Pulldown Resistance Input Capacitance CLOCK INPUTS (CLKP, CLKN) Differential Input Voltage Swing Sine wave Square wave >1.5 >0.5 VP-P CIN VIH VIL IIN VPD = VTORB = 3.3V -20 1 1.5 2.5 0.7 x DVDD3.3 0.3 x DVDD3.3 +20 V V A M pF tCH tCL VIH VIL VCMR RIN CIN (Note 7) -100 1.125 110 2.5 1.375 tSETUP tHOLD Referenced to rising edge of clock (Note 6) Referenced to rising edge of clock (Note 6) Latency to I output Latency to Q output CLKP, CLKN CLKP, CLKN -1.2 2.0 9 8 0.9 0.9 100 ns ns Clock Cycles ns ns mV mV V pF nOUT SYMBOL VREFIOCR RREFIO TCOREF tFALL tRISE tPD 90% to 10% (Note 5) 10% to 90% (Note 5) Excluding data latency (Note 5) Measured differentially IOUTFS = 2mA IOUTFS = 20mA CONDITIONS MIN 0.125 10 25 0.7 0.7 1.1 1 30 30 TYP MAX 1.260 UNITS V k ppm/C ns ns ns pV*s pA/Hz
ANALOG OUTPUT TIMING (See Figure 4)
LVDS LOGIC INPUTS (B15P/B15N-B0P/B0N, XORN, XORP, SELIQN, SELIQP)
4
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, output load 50 double-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Differential Input Slew Rate External Common-Mode Voltage Range Input Resistance Input Capacitance POWER SUPPLIES Analog Supply Voltage Range Digital Supply Voltage Range AVDD3.3 AVDD1.8 DVDD3.3 DVDD1.8 IAVDD3.3 IAVDD1.8 IDVDD3.3 IDVDD1.8 Power Dissipation Power-Supply Rejection Ratio PDISS PSRR fDAC = 250Msps, fOUT = 16MHz Power-down fDAC = 250Msps, fOUT = 16MHz Power-down fDAC = 250Msps, fOUT = 16MHz Power-down fDAC = 250Msps, fOUT = 16MHz Power-down fDAC = 250Msps, fOUT = 16MHz Power-down AVDD3.3 = AVCLK = DVDD3.3 = +3.3V 5% (Notes 8, 9) -0.1 3.135 1.710 3.135 1.710 3.3 1.8 3.3 1.8 52 1 32 1 0.2 1 36 4 296 16 +0.1 324 40 1 36 3.465 1.890 3.465 1.890 56 V V mA A mA A mA A mA A mW W %FS/V SYMBOL SRCLK VCOM RCLK CCLK (Note 8) CONDITIONS MIN TYP >100 AVCLK / 2 0.3 5 2.5 MAX UNITS V/s V k pF
MAX5878
Analog Supply Current
Digital Supply Current
Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design. Nominal full-scale current IOUTFS = 32 x IREF. This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5878. Parameter measured single-ended into a 50 termination resistor. Not production tested. Guaranteed by design. No termination resistance between XORP and XORN. A differential clock input slew rate of >100V/s is required to achieve the specified dynamic performance. Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.
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5
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
Typical Operating Characteristics
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 50Msps)
MAX5878 toc01
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 100Msps)
MAX5878 toc02
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 150Msps)
-6dBFS 80 0dBFS SFDR (dBc) 60 -12dBFS
MAX5878 toc03
100 -6dBFS 80 0dBFS SFDR (dBc) 60 -12dBFS
100 -6dBFS 80 -12dBFS SFDR (dBc) 60 0dBFS
100
40
40
40
20
20
20
0 0 5 10 15 20 25 fOUT (MHz)
0 0 10 20 30 40 50 fOUT (MHz)
0 0 15 30 45 60 75 fOUT (MHz)
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 200Msps)
MAX5878 toc04
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 250Msps)
MAX5878 toc05
TWO-TONE IMD vs. OUTPUT FREQUENCY (1MHz CARRIER SPACING, fCLK = 100Msps)
MAX5878 toc06
100 -6dBFS 80 0dBFS SFDR (dBc) -12dBFS
100 -6dBFS 80 0dBFS SFDR (dBc) 60 -12dBFS
-60
-70 TWO-TONE IMD (dBc)
60
-80
-6dBFS
40
40
-90
20
20
-100 -12dBFS
0 0 20 40 60 80 100 fOUT (MHz)
0 0 25 50 75 100 125 fOUT (MHz)
-110 5 10 15 20 25 30 35 40 fOUT (MHz)
6
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.)
TWO-TONE INTERMODULATION DISTORTION (fCLK = 100Msps)
MAX5878 toc07
TWO-TONE IMD vs. OUTPUT FREQUENCY (1MHz CARRIER SPACING, fCLK = 200Msps)
MAX5878 toc08
SFDR vs. FULL-SCALE OUTPUT CURRENT (fCLK = 200MHz)
AOUT = -6dBFS 20mA
MAX5878 toc09
0
BW = 12MHz
fT1 = 28.9795MHz fT2 = 30.0049MHz fT1 fT2
-40 -50 TWO-TONE IMD (dBc) -60 -70 -80 -90 -12dBFS -100 -6dBFS
100
-20 OUTPUT POWER (dBFS)
80 10mA
SFDR (dBc)
-40
60
5mA
-60 2 x fT1 - fT2 -80 2 x fT2 - fT1
40
20
-100 24 26 28 30 fOUT (MHz) 32 34 36
0 0 10 20 30 40 50 60 70 80 0 20 40 60 80 100 fOUT (MHz) fOUT (MHz)
SFDR vs. TEMPERATURE (fCLK = 250Msps)
MAX5878 toc10
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5878 toc11
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
3 2
MAX5878 toc12
85
AOUT = -6dBFS TA = +25C
3 2 1
4
80 SFDR (dBc) DNL (LSB) INL (LSB)
1 0 -1 -2
75
TA = -40C TA = +85C
0 -1
70 -2 65 0 25 50 75 100 125 fOUT (MHz) -3 0 16,384 32,768 49,152 65,536 DIGITAL INPUT CODE
-3 -4 0 16,384 32,768 49,152 65,536 DIGITAL INPUT CODE
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7
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.)
POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 10MHz)
MAX5878 toc13
POWER DISSIPATION vs. SUPPLY VOLTAGE (fCLK = 100Msps, fOUT = 10MHz)
AOUT = 0dBFS EXTERNAL REFERENCE
MAX5878 toc14
FOUR-TONE POWER RATIO PLOT (fCLK = 150MHz)
BW = 12MHz fT1 fT2 fT3 fT4
MAX5878 toc15
300 280 POWER DISSIPATION (mW) 260 240 220 200 180 0
230
0
AOUT = 0dBFS
POWER DISSIPATION (mW)
OUTPUT POWER (dBFS)
225
-20
-40 fT1 = 29.9433MHz fT2 = 30.8266MHz fT3 = 31.9087MHz fT4 = 32.9123MHz
220
-60
215 INTERNAL REFERENCE 210 3.135
-80
-100 3.3 SUPPLY VOLTAGE (V) 3.465 26 28 30 32 fOUT (MHz) 34 36 38
50
100
150
200
250
fCLK (Msps)
ACLR FOR W-CDMA MODULATION, SINGLE CARRIER ACLR
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 DC 9.2MHz/div
MAX5878 toc16
ACLR FOR W-CDMA MODULATION TWO CARRIER ACLR
-30 ANALOG OUTPUT POWER (dBm) -40 -50 -60 -70 -80 -90 -100 -110 -120 fCLK = 245.76Msps fCENTER = 30.72MHz ACLR = +78dB
MAX5878 toc17
ANALOG OUTPUT POWER (dBm)
fCLK = 184.32MHz fCARRIER = 30.72MHz ACLR = +80dB
-20
92.16MHz
3.05MHz/div
-30 ANALOG OUTPUT POWER (dBm) -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
fCLK = 184.32Msps fCENTER = 30.72MHz ACLR = +77dB
MAX5878 toc18
83 82 ACLR (dB) 81 80 81.4
82.7 82.3
83.0
ADJACENT ALTERNATE 80.7 80.4 79.0 79.0
79 78 77 76 1 3.05MHz/div 2 3 4 NUMBER OF CHANNELS
8
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MAX5878 toc19
ACLR FOR W-CDMA MODULATION TWO CARRIER ACLR
W-CDMA BASEBAND ACLR
84
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10, 12, 13, 15, 20, 23, 26, 27, 30, 33, 36 11 14, 21, 22, 31, 32 16 17 18 19, 34 24 25 28 29 35 37 38 NAME B4N B3P B3N B2P B2N B1P B1N B0P B0N GND Complementary Data Bit 4 Data Bit 3 Complementary Data Bit 3 Data Bit 2 Complementary Data Bit 2 Data Bit 1 Complementary Data Bit 1 Data Bit 0 (LSB) Complementary Data Bit 0 (LSB) Ground Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to GND. Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with a 0.1F capacitor to GND. Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1F capacitor to GND. REFIO can be driven with an external reference source. See Table 1. Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA fullscale output current, connect a 2k resistor between FSADJ and DACREF. See Table 1. Current-Set Resistor Return Path. Internally connected to GND. Do not use as an external ground connection. Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a 0.1F capacitor to GND. Complementary Q-DAC Output. Negative terminal for current output. Q-DAC Output. Positive terminal for current output. Complementary I-DAC Output. Negative terminal for current output. I-DAC Output. Positive terminal for current output. Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to GND. Complementary Converter Clock Input. Negative input terminal for differential converter clock. Internally biased to AVCLK / 2. Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to AVCLK / 2. Two's-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two'scomplement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format. TORB has an internal pulldown resistor. FUNCTION
MAX5878
DVDD3.3 AVDD3.3 REFIO FSADJ DACREF AVDD1.8 OUTQN OUTQP OUTIN OUTIP AVCLK CLKN CLKP
39
TORB
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9
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
Pin Description (continued)
PIN 40 NAME PD FUNCTION Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode. Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor. Complementary LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow the data stream to pass unchanged to the DAC input. Set XORN low and XORP high to invert the DAC input data. If unused, connect XORN to DVDD1.8. LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow the data stream to pass unchanged to the DAC input. Set XORN low and XORP high to invert the DAC input data. If unused, connect XORP to GND. LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the I-DAC outputs. Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs. Complementary LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the I-DAC outputs. Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs. Data Bit 15 (MSB) Complementary Data Bit 15 (MSB) Data Bit 14 Complementary Data Bit 14 Data Bit 13 Complementary Data Bit 13 Data Bit 12 Complementary Data Bit 12 Data Bit 11 Complementary Data Bit 11 Data Bit 10 Complementary Data Bit 10 Data Bit 9 Complementary Data Bit 9 Data Bit 8 Complementary Data Bit 8 Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1F capacitor to GND. Data Bit 7 Complementary Data Bit 7 Data Bit 6 Complementary Data Bit 6 Data Bit 5 Complementary Data Bit 5 Data Bit 4 Exposed Pad. Must be connected to GND through a low-impedance path.
41
XORN
42
XORP
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 --
SELIQP SELIQN B15P B15N B14P B14N B13P B13N B12P B12N B11P B11N B10P B10N B9P B9N B8P B8N DVDD1.8 B7P B7N B6P B6N B5P B5N B4P EP
10
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
Detailed Description
Architecture
The MAX5878 high-performance, 16-bit, dual currentsteering DAC (Figure 1) operates with DAC update rates up to 250Msps. The converter consists of input registers and a demultiplexer for single-port operation, followed by a current-steering array. During operation, the input data registers demultiplex the single-port data bus. The current-steering array generates differential full-scale currents in the 2mA to 20mA range. An internal current-switching network, in combination with external 50 termination resistors, converts the differential output currents into dual differential output voltages with a 0.1V to 1V peak-to-peak output voltage range. An integrated +1.2V bandgap reference, control amplifier, and userselectable external resistor determine the data converter's full-scale output range.
Reference Architecture and Operation
The MAX5878 supports operation with the internal +1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, low-impedance reference source. REFIO also serves as a reference output when the DAC operates in internal reference mode. For stable operation with the internal reference, decouple REFIO to GND with a 1F capacitor. Due to its limited output drive capability, buffer REFIO with an external amplifier when driving large external loads.
DVDD3.3
DVDD1.8
AVDD1.8
AVDD3.3 OUTIP
TORB SELIQP SELIQN DATA15- DATA0 XORP XORN LATCH XOR/ DECODE LATCH LATCH DAC OUTQN AVCLK CLKP CLKN CLK INTERFACE DACREF +1.2V REFERENCE REFIO FSADJ LVDS RECEIVER LATCH OUTQP LATCH XOR/ DECODE LATCH LATCH DAC OUTIN
MAX5878
POWER-DOWN BLOCK
PD
GND
Figure 1. MAX5878 High-Performance, 16-Bit, Dual Current-Steering DAC
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11
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
The MAX5878's reference circuit (Figure 2) employs a control amplifier to regulate the full-scale current IOUTFS for the differential current outputs of the DAC. Calculate the full-scale output current as follows: IOUTFS = 32 x VREFIO 1 x 1 - 16 RSET 2
Clock Inputs (CLKP, CLKN)
The MAX5878 features flexible differential clock inputs (CLKP, CLKN) operating from a separate supply (AVCLK) to achieve optimum jitter performance. Drive the differential clock inputs from a single-ended or a differential clock source. For single-ended operation, drive CLKP with a logic source and bypass CLKN to GND with a 0.1F capacitor. CLKP and CLKN are internally biased to AVCLK / 2. This facilitates the AC-coupling of clock sources directly to the device without external resistors to define the DC level. The dynamic input resistance from CLKP and CLKN to ground is 5k.
where I OUTFS is the full-scale output current of the DAC. R SET (located between FSADJ and DACREF) determines the amplifier's full-scale output current for the DAC. See Table 1 for a matrix of different IOUTFS and RSET selections.
Analog Outputs (OUTIP, OUTIN, OUTQP, OUTQN)
Each MAX5878 DAC outputs two complementary currents (OUTIP/N, OUTQP/N) that operate in a singleended or differential configuration. A load resistor converts these two output currents into complementary single-ended output voltages. A transformer or a differential amplifier configuration converts the differential voltage existing between OUTIP (OUTQP) and OUTIN (OUTQN) to a single-ended voltage. If not using a transformer, the recommended termination from the output is a 25 termination resistor to ground and a 50 resistor between the outputs. To generate a single-ended output, select OUTIP (or OUTQP) as the output and connect OUTIN (or OUTQN) to GND. SFDR degrades with single-ended operation or increased output swing. Figure 3 displays a simplified diagram of the internal output structure of the MAX5878.
+1.2V REFERENCE
Table 1. IOUTFS and RSET Selection Matrix Based on a Typical +1.200V Reference Voltage
FULL-SCALE CURRENT IOUTFS (mA) 2 5 10 15 20 RSET () CALCULATED 19.2k 7.68k 3.84k 2.56k 1.92k 1% EIA STD 19.1k 7.5k 3.83k 2.55k 1.91k
AVDD CURRENT SOURCES CURRENT SWITCHES
10k REFIO 1F OUTIP FSADJ IREF RSET DACREF IREF = VREFIO / RSET GND CURRENT-SOURCE ARRAY DAC OUTIN
IOUT OUTIN OUTIP
IOUT
Figure 2. Reference Architecture, Internal Reference Configuration 12
Figure 3. Simplified Analog Output Structure
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
CLKP-CLKN
DATAIN
I0
Q0
I1
Q1
I2
Q2
I3
Q3
SELIQP
SELIQN tS tH I0 - 5 OUTI I0 - 6 I0 - 4 I0 - 3 I0 - 2
OUTQ
Q0 - 6 tPD
Q0 - 5 Q0 - 4 Q0 - 3 Q0 - 2
Figure 4. Timing Diagram
Data Timing Relationship
Figure 4 displays the timing relationship between digital LVDS data, clock, and output signals. The MAX5878 features a 2.0ns hold, a -1.2ns setup, and a 1.1ns propagation delay time. A nine (eight)-clock-cycle latency exists between CLKP/CLKN and OUTIP/OUTIN (OUTQP/OUTQN).
LVDS-Compatible Digital Inputs (B15P/B15N-B0P/B0N, XORP, XORN, SELIQP, SELIQN)
The MAX5878 latches B15P/N-B0P/N, XORP/N, and SELIQP/N data on the rising edge of the clock. A logichigh signal on SELIQP and a logic-low signal on SELIQN directs data onto the I-DAC inputs. A logic-low signal on SELIQP and a logic-high signal on SELIQN directs data onto the Q-DAC inputs. The MAX5878 features LVDS receivers on the bus input interface with internal 110 termination resistors. See
Figure 5. XORP and XORN are not internally terminated. These LVDS inputs (B15P/N-B0P/N) allow for a low differential voltage swing with low constant power consumption. A 1.25V common-mode level and 250mV differential input swing can be applied to the B15P/N-B0P/N, XORP/N, and SELIQP/N inputs. The MAX5878 includes LVDS-compatible exclusive-OR inputs (XORP, XORN). Input data (all bits) is compared with the bits applied to XORP and XORN through exclusive-OR gates. Setting XORP high and XORN low inverts the input data. Setting XORP low and XORN high leaves the input data noninverted. By applying a previously encoded pseudo-random bit stream to the data input and applying decoding to XORP/XORN, the digital input data can be decorrelated from the DAC output, allowing for the troubleshooting of possible spurious or harmonic distortion degradation due to digital feedthrough on the PC board. If XOR functionality is not required, connect XORP to GND and XORN to DVDD1.8.
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
Table 2. DAC Output Code Table
DIGITAL INPUT CODE OFFSET BINARY 0000 0000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 TWO'S COMPLEMENT 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 OUT_P 0 IOUTFS / 2 IOUTFS OUT_N IOUTFS IOUTFS / 2 0
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB) The TORB input selects between two's-complement or offset binary digital input data. Set TORB to a CMOSlogic-high level to indicate a two's-complement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format. Power-Down Operation (PD) The MAX5878 also features an active-high power-down mode that reduces the DAC's digital current consumption from 36.2mA to less than 5A and the analog current consumption from 84mA to less than 2A. Set PD high to power down the MAX5878. Set PD low for normal operation. When powered down, the MAX5878 reduces the overall power consumption to less than 16W. The MAX5878 requires 10ms to wake up from power-down and enter a fully operational state. The PD integrated pulldown resistor activates the MAX5878 if PD is left floating.
Applications Information
CLK Interface
The MAX5878 features a flexible differential clock input (CLKP, CLKN) with a separate supply (AV CLK ) to achieve optimum jitter performance. Use an ultra-low jitter clock to achieve the required noise density. Clock jitter must be less than 0.5psRMS for meeting the specified noise density. For that reason, the CLKP/CLKN input source must be designed carefully. The differential clock (CLKN and CLKP) input can be driven from a single-ended or a differential clock source. Differential clock drive is required to achieve the best dynamic performance from the DAC. For single-ended operation, drive CLKP with a low noise source and bypass CLKN to GND with a 0.1F capacitor. Figure 6 shows a convenient and quick way to apply a differential signal created from a single-ended source (e.g., HP 8662A signal generator) and a wideband transformer. Alternatively, these inputs can be driven from a CMOS-compatible clock source; however, it is recommended to use sinewave or AC-coupled differential ECL/PECL or LVDS drive for best dynamic performance.
WIDEBAND RF TRANSFORMER PERFORMS SINGLE-ENDED-TODIFFERENTIAL CONVERSION 25
B15P-B0P, SELIQP 110 B15N-B0N, SELIQN
MAX5878
0.1F CLKP
D
Q TO DECODE LOGIC
SINGLE-ENDED CLOCK SOURCE (e.g., HP 8662A)
1:1 25 0.1F
TO DAC
D
Q
CLKN
CLOCK
GND
Figure 5. Simplified LVDS-Compatible Digital Input Structure 14
Figure 6. Differential Clock-Signal Generation
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
Differential-to-Single-Ended Conversion Using a Wideband RF Transformer
Use a pair of transformers (Figure 7) or a differential amplifier configuration to convert the differential voltage existing between OUTIP/OUTQP and OUTIN/OUTQN to a single-ended voltage. Optimize the dynamic performance by using a differential transformer-coupled output and limit the output power to <0dBm full scale. Pay close attention to the transformer core saturation characteristics when selecting a transformer for the MAX5878. Transformer core saturation can introduce strong 2nd-order harmonic distortion especially at low output frequencies and high signal amplitudes. For best results, center tap the transformer to ground. When not using a transformer, terminate each DAC output to ground with a 25 resistor. Additionally, place a 50 resistor between the outputs (Figure 8). For a single-ended unipolar output, select OUTIP (OUTQP) as the output and ground OUTIN (OUTQN) to GND. Driving the MAX5878 single-ended is not recommended since additional noise and distortion will be added. The distortion performance of the DAC depends on the load impedance. The MAX5878 is optimized for 50 differential double termination. It can be used with a transformer output as shown in Figure 7 or just one 25 resistor from each output to ground and one 50 resistor between the outputs (Figure 8). This produces a fullscale output power of up to -2dBm, depending on the output current setting. Higher termination impedance can be used at the cost of degraded distortion performance and increased output noise voltage.
Grounding, Bypassing, and PowerSupply Considerations
Grounding and power-supply decoupling can strongly influence the MAX5878 performance. Unwanted digital crosstalk couples through the input, reference, power supply, and ground connections, and affects dynamic performance. High-speed, high-frequency applications require closely followed proper grounding and powersupply decoupling. These techniques reduce EMI and internal crosstalk that can significantly affect the MAX5878 dynamic performance. Use a multilayer printed circuit (PC) board with separate ground and power-supply planes. Run high-speed signals on lines directly above the ground plane. Keep digital signals as far away from sensitive analog inputs and outputs, reference input sense lines, commonmode input, and clock inputs as practical. Use a symmetric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus optimizing the DAC's dynamic performance. Keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches. The MAX5878 requires five separate power-supply inputs for analog (AV DD1.8 and AV DD3.3 ), digital (DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry. All power-supply pins must be connected to their proper supply. Decouple each AVDD, DVDD, and AVCLK input pin with a separate 0.1F capacitor as close to the device as possible with the shortest possible connection to the ground plane (Figure 9). Minimize the analog and digital load capacitances for optimized operation. Decouple all three power-supply voltages at the point they enter the PC board with tantalum or electrolytic
MAX5878
50 DATA15-DATA0 OUTIP/OUTQP 100 T2, 1:1
VOUT, SINGLE-ENDED
MAX5878
16 OUTIN/OUTQN
T1, 1:1 50
GND
WIDEBAND RF TRANSFORMER T2 PERFORMS THE DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
Figure 7. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer
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15
16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
capacitors. Ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. The analog and digital power-supply inputs AV DD3.3, AVCLK, and DVDD3.3 allow a +3.135V to +3.465V supply voltage range. The analog and digital power-supply inputs AVDD1.8 and DVDD1.8 allow a +1.71V to +1.89V supply voltage range. The MAX5878 is packaged in a 68-pin QFN-EP package, providing greater design flexibility, increased thermal efficiency, and optimized DAC AC performance. The EP enables the use of necessary grounding techniques to ensure highest performance operation. Thermal efficiency is not the key factor, since the MAX5878 features low-power operation. The exposed pad ensures a solid ground connection between the DAC and the PC board's ground layer. The data converter die attaches to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows for a solid attachment of the package to the PC board with standard infrared reflow (IR) soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (6mm x 6mm), ensures the proper attachment and grounding of the DAC. Designing vias into the land area and implementing large ground planes in the PC board design allow for the highest performance operation of the DAC. Use an array of at least 4 x 4 vias (0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 68-pin QFN-EP package. Connect the MAX5878 exposed paddle to GND. Vias connect the land pattern to internal or external copper planes. Use as many vias as possible to the ground plane to minimize inductance.
Static Performance Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees a monotonic transfer function. Offset Error The offset error is the difference between the ideal and the actual offset current. For a DAC, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the DAC. This error affects all codes by the same amount. Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.
BYPASSING--DAC LEVEL AVDD1.8 AVDD3.3 AVCLK
0.1F
0.1F
0.1F
DATA15-DATA0
OUTIP/OUTQP
25 DATA15-DATA0 OUTIP/OUTQP 50 OUTP 16
MAX5878
OUTIN/OUTQN
MAX5878
16 OUTIN/OUTQN
0.1F OUTN 25
0.1F
GND
DVDD1.8
DVDD3.3
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
Figure 8. Differential Output Configuration
Figure 9. Recommended Power-Supply Decoupling and Bypassing Circuitry
16
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum can be derived from the DAC's resolution (N bits): SNRdB = 6.02dB x N + 1.76dB However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading; therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Noise Spectral Density The DAC output noise floor is the sum of the quantization noise and the output amplifier noise (thermal and shot noise). Noise spectral density is the noise power in 1Hz bandwidth, specified in dBFS/Hz. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of their next-largest distortion component. SFDR is usually measured in dBc and with respect to the carrier frequency amplitude or in dBFS with respect to the DAC's full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Two-/Four-Tone Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc (or dBFS) of the worst 3rd-order (or higher) IMD product(s) to either output tone; 2nd-order IMD products usually fall at frequencies that digital filtering easily removes. Therefore, they are not as critical as 3rd-order IMDs. The two-tone IMD performance of the MAX5878 is tested with the two individual output tone levels set to at least -6dBFS and the four-tone performance was tested according to the GSM model at an output frequency of 16MHz and amplitude of -12dBFS. Adjacent Channel Leakage Power Ratio (ACLR) Commonly used in combination with wideband codedivision multiple-access (W-CDMA), ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV*s.
MAX5878
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16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs MAX5878
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
68L QFN.EPS
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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